1. Field of the Invention
The present invention relates to communication transceiver clock and data recovery, and, in particular, to timing recovery when oversampling lower data rates.
2. Description of the Related Art
In many data communication applications, serializer and de-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data. One application for SerDes devices is related to the Universal Serial Bus (USB) specification that establishes communication between host controllers and multiple devices.
The USB standard currently includes three specifications: USB 1.x (“USB1”), USB 2.x (“USB2”), and USB 3.x (“USB3”), where “x” implies a particular version of the specification. USB1 specifies data transfer rates of 1.5 Mbps and 12 Mbps. USB2 specifies a higher data transfer rate of 480 Mbps, and USB3 specifies an even higher data transfer rate of 5 Gbps, termed a “SuperSpeed” bus. A SerDes device operating in accordance with USB3 desirably supports the lower speed specifications of USB1 and USB2, and so must support these data transfer rates (0.48 Gbps, 0.012 Gbps and 0.0015 Gbps). In addition, USB devices often interface with remote or network devices conforming to the Serial Advanced Technology Attachment (SATA) specification and their associated data stream rates. However, a SerDes device implementation supporting such a wide range of data transfer rates faces numerous technical challenges.
One component of a SerDes device is a clock and data recovery (CDR) circuit. The CDR extracts and reconstructs clock and data information from a single data stream that doesn't contain a clock signal during serial data transmission. The receiver of the data stream generates a signal, and then aligns sampling of the data stream with timing of detected transitions in the data stream based on a locally generated clock using a phase-locked loop. In operation at high data rates, SerDes devices are challenged with correctly extracting such timing of the data stream due to jitter, noise, and other effects of the communication channel. Equalization (analog and decision feedback) is often employed, requiring adaptation during acquisition and steady state operation. These factors often dictate that SerDes receiver design, including the CDR circuit, be optimized for a given, relatively narrow range of data transfer rates. Consequently, many existing SerDes designs incorporate separate CDR circuitry to support such a wide range of data transfer rates as specified in USB3.
Backward compatibility for each new standard often requires the new devices operating with the standard support operation in accordance with previous versions of the standard. Unfortunately, to accommodate such a wide range of operating frequencies with USB1, USB2 and USB3, separate receivers operating in parallel is often required.